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Espressif Systems /ESP32-C6 /I2C0 /SCL_STOP_SETUP

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Interpret as SCL_STOP_SETUP

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31282724232019161512118743000000000000000000000000000000000000000000TIME

Description

Configures the delay between the SDA and SCL positive edge for a stop condition

Fields

TIME

This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data